Altera Stratix V Advanced Systems Development Board - Manual (Page 40)

2–30 Chapter 2: Board Components
Components and Interfaces
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
Components and Interfaces
This section describes the development board's communication ports and interface
cards relative to the Stratix V GX FPGA devices. The development board supports the
following communication ports:
■ PCI Express
■ FMC
■ HSMC
PCI Express
The Stratix V Advanced Systems development board is designed to fit entirely into a
PC motherboard with a ×16 PCI Express slot that can accommodate a full height long
form factor add-in card. This interface uses two Stratix V GX FPGA devices
PCI Express hard IP block, saving logic resources for the user logic application.
PCI Express x16 is achieved using a PLX PEX8747 PCIe switch to multiplex x16
PCI Express data to x8 PCI Express data to each Stratix V GX FPGA device.
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For more information on using the PCI Express hard IP block, refer to the IP Compiler
for PCI Express User Guide .
The PCI Express interface supports auto-negotiating channel width from ×1 to ×4 to
×8 to ×16 as well as the connection speed of Gen1 at 2.5 Gbps/lane, Gen2 at 5.0
Gbps/lane, or Gen3 at 8.0 Gbps/lane for a maximum of 128 Gbps full-duplex
bandwidth.
The power for the board can be sourced entirely from the PCI Express edge connector
when installed into a PC motherboard. Some applications may also require additional
power from the PCI Express 2x4 ATX power connector (J10). Although the board can
also be powered by a laptop power supply for use on a lab bench, it is not
recommended to power from both the PCI Express edge connector and the laptop
supplies at the same time. Ideal diode power sharing devices have been designed into
this board to prevent damages or back-current from one supply to the other.
The PCIE_REFCLK_P/N signal is a 100-MHz differential input that is driven from the PC
motherboard to the board through the PCI Express edge connector. This signal
connects through a fan out buffer to both Stratix V FPGAs and the PLX switch REFCLK
input pin pairs. DC coupling on the clock signals is built into the PCI Express clock
buffer. This clock is terminated on the motherboard and therefore, no on-board
termination is required. This clock can have spread-spectrum properties that change
its period between 9.847 ps to 10.203 ps. The I/O standard is High-Speed Current
Steering Logic (HCSL).