Altera Stratix V Advanced Systems Development Board - Manual (Page 65)

Chapter 2: Board Components 2–55
Memory
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
K10 D3 1.5-V HSTL Class I AU18 AE13 D30 L33 Write data bus
J11 D4 1.5-V HSTL Class I AR19 AF10 A32 V35 Write data bus
G11 D5 1.5-V HSTL Class I AP19 AE12 E30 R34 Write data bus
E10 D6 1.5-V HSTL Class I AM17 AE9 D32 R33 Write data bus
D11 D7 1.5-V HSTL Class I AM19 AE10 E32 W34 Write data bus
C11 D8 1.5-V HSTL Class I AL19 AE11 F31 T34 Write data bus
B3 D9 1.5-V HSTL Class I AG17 AG13 Y28 J34 Write data bus
C3 D10 1.5-V HSTL Class I AG18 AE14 Y29 J33 Write data bus
D2 D11 1.5-V HSTL Class I AJ17 AW10 Y30 H35 Write data bus
F3 D12 1.5-V HSTL Class I AK17 AF14 Y27 J31 Write data bus
G2 D13 1.5-V HSTL Class I AK18 AY10 V29 G35 Write data bus
J3 D14 1.5-V HSTL Class I AL17 BA10 W28 G34 Write data bus
L3 D15 1.5-V HSTL Class I AL18 AY12 U29 F35 Write data bus
M3 D16 1.5-V HSTL Class I AN19 BA12 V28 F34 Write data bus
N2 D17 1.5-V HSTL Class I AN20 BB12 G31 E35 Write data bus
H1 DOFFN 1.5-V HSTL Class I AP18 AP12 K29 A37 PLL disable
A6 K_N
Differential 1.5-V
HSTL Class I
AJ16 BD11 R28 H33 Write clock
B6 K_P
Differential 1.5-V
HSTL Class I
AJ15 BC11 T28 H34 Write clock
R6 ODT — — — — —
On-die termination,
resistor grounded
P11 Q0 1.5-V HSTL Class I BD16 AR15 N29 P36 Read data bus
M10 Q1 1.5-V HSTL Class I BD13 AU14 P30 N37 Read data bus
L11 Q2 1.5-V HSTL Class I BC16 AM16 L29 P37 Read data bus
K11 Q3 1.5-V HSTL Class I BC13 AM14 M30 P38 Read data bus
J10 Q4 1.5-V HSTL Class I BB15 AU13 L30 N38 Read data bus
F11 Q5 1.5-V HSTL Class I BB14 AL16 H31 P39 Read data bus
E11 Q6 1.5-V HSTL Class I BA13 AL15 F32 U36 Read data bus
C10 Q7 1.5-V HSTL Class I AK15 AL14 G32 T36 Read data bus
B11 Q8 1.5-V HSTL Class I AY13 AK14 H32 V36 Read data bus
B2 Q9 1.5-V HSTL Class I AE16 AR14 V31 W35 Read data bus
D3 Q10 1.5-V HSTL Class I AE15 AN15 W31 G37 Read data bus
E3 Q11 1.5-V HSTL Class I AE18 AN14 W32 F36 Read data bus
F2 Q12 1.5-V HSTL Class I AE17 AT15 Y32 D37 Read data bus
G3 Q13 1.5-V HSTL Class I AF16 AT14 T31 B39 Read data bus
K3 Q14 1.5-V HSTL Class I AG14 AU15 U30 B38 Read data bus
L2 Q15 1.5-V HSTL Class I AG15 AV14 R31 C37 Read data bus
N3 Q16 1.5-V HSTL Class I AJ14 AW13 P31 A38 Read data bus
Table 2–25. FPGA1 QDRII+ Pin Assignments, Signal Names and Functions (Part 2 of 3)
Board
Reference
Schematic
Signal Name
I/O Standard
Stratix V GX FPGA1 Device Pin Number
Description
QDR2A QDR2B QDR2C QDR2D