Altera Stratix V Advanced Systems Development Board - Manual (Page 77)

Chapter 2: Board Components 2–67
Power Supply
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
Power Measurement
There are 16 power supply rails which have on-board voltage, current, and wattage
sense capabilities. The 8-channel differential 24-bit ADC device and rails are split
from the primary supply plane by a low-value sense resistor for the ADC to measure
voltage and current. A serial peripheral interface (SPI) bus connects the ADC device
to the MAX V CPLD System Controller.
Figure 2–9 shows the block diagram for the power measurement circuitry.
Table 2–30 lists the targeted rails. The schematic signal name specifies the name of the
rail being measured and the device pin specifies the devices attached to the rail. If no
subnet is named, the power is the total output power for that voltage.
Figure 2–9. Power Measurement Circuit
SCK
DSI
DSO
CSn
8 Ch.
Power Supply Load 0-7
Supply
0-7
R
SENSE
5M2210
LTC2418
EPM570
USB
PHY
To User PC
Power GUI
JTAG Chain
SPI Bus
On-Board
USB-Blaster II
Feedback
Table 2–30. Power Rail Measurements Based on the GUI Selection
Number
Schematic Signal
Name
Voltage (V) Device Pin Description
0 S5A_VCCPD_PGM 2.50
VCCPD FPGA1 I/O pre-drivers
VCCPGM FPGA1 configuration I/O
1 S5_VCCIO_1.5V 1.50
VCCIO3[B:E] FPGA1 and FPGA2 VCCIO banks
VCCIO4[B:E] FPGA1 and FPGA2 VCCIO banks
VCCIO7[C:E] FPGA1 and FPGA2 VCCIO banks
VCCIO8[A:E] FPGA1 and FPGA2 VCCIO banks
2 S5B_VCCR_GXB 1.00 VCCR_GXB FPGA2 XCVR analog receive
3 S5_VCC 0.90
VCC FPGA1 and FPGA2 core and periphery power
VCCHIP_[L,R] FPGA1 and FPGA2 PCI Express Hard IP digital power
VCCHSSI_[L,R] FPGA1 and FPGA2 XVCR PCS power
4 S5B_VCCPD_PGM 2.50
VCCPD FPGA2 I/O pre-drivers
VCCPGM FPGA2 configuration I/O
5 S5_VCCIO_2.5V 2.50 VCCIO4A FPGA1 and FPGA2 VCCIO bank 4A
6 S5A_VCCR_GXB 1.00 VCCR_GXB FPGA1 XCVR analog receive
7 — — — —