Rainbow Electronics AT91CAP9S250A - Manual (Page 150)

150
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
21.5.1 Bus Multiplexing
The EBI offers a complete set of control signals that share the 32-bit data lines, the address
lines of up to 26 bits and the control signals through a multiplex logic operating in function of
the memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address
and output control lines at a stable state while no external access is being performed. Multi-
plexing is also designed to respect the data float times defined in the Memory Controllers.
Furthermore, refresh cycles of the SDRAM are executed independently by the SDRAM Con-
troller without delaying the other external Memory Controller accesses.
21.5.2 Pull-up Control
The EBI_CSA registers in the Chip Configuration User Interface permit enabling of on-chip
pull-up resistors on the data bus lines not multiplexed with the PIO Controller lines. The pull-up
resistors are enabled after reset. Setting the DBPUC bit disables the pull-up resistors on the
D0 to D15 lines. Enabling the pull-up resistor on the D16-D31 lines can be performed by pro-
gramming the appropriate PIO controller.
21.5.3 Supply Control
The EBI I/O pads may be supplied with two different voltage (3.3V or 1.8V). The EBI_CSA reg-
isters in the Chip Configuration User Interface allows to choose between the two different
voltages. At power-up, the selected supply control is 3.3V, allowing the EBI to work at low sys-
tem speed even supplied at 1.8V.
21.5.4 Static Memory Controller
For information on the Static Memory Controller, refer to the section “Static Memory
Controller”.
21.5.5 DDR/SDRAM Controller
For information on the DDR/SDRAM Controller, refer to the section “DDR/SDRAM”.
21.5.6 BCRAM Controller
For information on the BCRAM Controller, refer to the section “BCRAM”.
21.5.7 ECC Controller
For information on the ECC Controller, refer to the section “ECC” .
21.5.8 CompactFlash Support
The External Bus Interface integrates circuitry that interfaces to CompactFlash devices.
The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or
NCS5 address space. Programming the EBI_CS4A and/or EBI_CS5A bit of the EBI_CSA
Register in the Chip Configuration User Interface to the appropriate value enables this logic.
For details on this register, refer to the section “Bus Matrix”.
Access to an external Compact-
Flash device is then made by accessing the address space reserved for NCS4 and/or NCS5
(i.e., between 0x5000 0000 and 0x5FFF FFFF for NCS4 and between 0x6000 0000 and
0x6FFF FFFF for NCS5).
All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are sup-
ported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are
not handled.