Rainbow Electronics AT91CAP9S250A - Manual (Page 353)

353
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
The PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that
depends on the respective source signal frequency and on the parameters DIV and MUL. The
factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the
corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLL can be
performed by writing a value higher than 0 in the MUL field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit (LOCKA or
LOCKB) in PMC_SR is automatically cleared. The values written in the PLLCOUNT field (PLLA-
COUNT or PLLBCOUNT) in CKGR_PLLR (CKGR_PLLAR or CKGR_PLLBR) ,are loaded in the
PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it reaches 0.
At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The
user has to load the number of Slow Clock cycles required to cover the PLL transient time into
the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL
and its target frequency can be calculated using a specific tool provided by Atmel.
28.4.3 UTMI Phase Lock Loop Programming
The multiplier is hard-wired to 40 to obtain the USB High Speed 480 MHz.
Figure 28-6. UTMI PLL
Whenever the PLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR
is automatically cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded
in the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it
reaches 0. At this time, the LOCKU bit is set in PMC_SR and can trigger an interrupt to the pro-
cessor. The user has to load the number of Slow Clock cycles required to cover the PLL
transient time into the PLLCOUNT field.
PLL
PLLCOUNT
LOCKU
UPLLEN
SLCK
MAINCK USBHSCK
PLL
Counter