Rainbow Electronics AT91CAP9S250A - Manual (Page 221)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
23.4.2 SDRAM Controller Read Cycle
The DDRSDRC allows burst access or single access in normal mode (mode =000). Whatever
access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing perfor-
mance of the DDRSDRC.
The SDRAM devices are programmed with a burst length equal to 8 which determines the length
of a sequential data output by the read command that is set to 8. The latency from read com-
mand to data output is equal to 2, 2.5 or 3. This value is programmed during the initialization
phase (see
Section 23.3.1 ”SDR-SDRAM Initialization” on page 213 ).
To initiate a single access, the DDRSDRC checks if the page access is already open. If
row/bank addresses match with the previous row/bank addresses, the controller generates a
read command. If the bank addresses are not identical or if bank addresses are identical but the
row addresses are not identical, the controller generates a precharge command, activates the
new row and initiates a read command. To comply with SDRAM timing parameters, additional
clock cycles are inserted between precharge/active (Trp) commands and active/read (T rcd)
command. After a read command, additional wait states are generated to comply with cas
latency. The DDRSDRC supports a cas latency of two, two and half, and three (2 or 3 clocks
delay). As the burst length is fixed to 8, in the case of single access or burst access inferior to 8
data requests, it has to stop the burst otherwise seven or X values could be read. Burst Stop
Command (BST) is used to stop output during a burst read.
To initiate a burst access, the DDRSDRC checks the transfer type signal. If the next accesses
are sequential read accesses, reading to the SDRAM device is carried out. If the next access is
a read non-sequential access, then an automatic page break can be inserted. If the bank
addresses are not identical or if bank addresses are identical but the row addresses are not
identical, the controller generates a precharge command, activates the new row and initiates a
read command. In the case where the page access is already open, a read command is
generated.
To comply with SDRAM timing parameters, additional clock cycles are inserted between pre-
charge/active (Trp) commands and active/read (Trcd) commands. The DDRSDRC supports a
cas latency of two, two and half, and three (2 or 3 clocks delay). During this delay, the controller
uses internal signals to anticipate the next access and improve the performance of the control-
ler. Depending on the latency(2/2.5/3), the DDRSDRC anticipates 2 or 3 read accesses. In the
case of burst of specified length, accesses are not anticipated, but if the burst is broken (border,
busy mode, etc.), the next access is treated as an incrementing burst of unspecified length, and
in function of the latency(2/2.5/3), the DDRSDRAMC anticipates 2 or 3 read accesses.
For a definition of timing parameters, refer to Section 23.6.3 ”DDRSDRC Configuration Register”
on page 235 .
Read accesses to the SDRAM are burst oriented and the burst length is programmed to 8. It
determines the maximum number of column locations that can be accessed for a given read
command. When the read command is issued, 8 columns are selected. All accesses for that
burst take place within these eight columns, meaning that the burst wraps within these 8 col-
umns if the boundary is reached. These 8 columns are selected by addr[13:3]; addr[2:0] is used
to select the starting location within the block.
In the case of incrementing burst (INCR/INCR4/INCR8/INCR16), the addresses can cross the
16-byte boundary of the SDRAM device. For example, when a transfer (INCR4) starts at
address 0x0C, the next access is 0x10, but since the burst length is programmed to 8, the next
access is 0x00. Since the boundary is reached, the burst wraps. The DDRSDRC takes into