Rainbow Electronics AT91CAP9S250A - Manual (Page 360)

360
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Once the PMC_PCKx register has been programmed, The corresponding programmable
clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in
the PMC_SR register. This can be done either by polling the status register or by waiting the
interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the
PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write
operation.
If the CSS and PRES parameters are to be modified, the corresponding programmable
clock must be disabled first. The parameters can then be modified. Once this has been
done, the user must re-enable the programmable clock and wait for the PCKRDYx bit to be
set.
Code Example:
write_register(PMC_PCK0,0x00000015)
Programmable clock 0 is main clock divided by 32.
7. Enabling Peripheral Clocks
Once all of the previous steps have been completed, the peripheral clocks can be enabled
and/or disabled via registers PMC_PCER and PMC_PCDR.
Depending on the system used, PMC_APB_PERIPH_NB peripheral clocks can be enabled
or disabled. The PMC_PCSR provides a clear view as to which peripheral clock is enabled.
Note: Each enabled peripheral clock corresponds to Master Clock.
Code Examples:
write_register(PMC_PCER,0x00000110)
Peripheral clocks 4 and 8 are enabled.
write_register(PMC_PCDR,0x00000010)
Peripheral clock 4 is disabled.
29.8 Clock Switching Details
29.8.1 Master Clock Switching Timings
Table 29-1 and Table 29-2 give the worst case timings required for the Master Clock to switch
from one selected clock to another one. This is in the event that the prescaler is de-activated.