Rainbow Electronics AT91CAP9S250A - Manual (Page 468)

468
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
33.6.4 SPI Slave Mode
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI
clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master.
When NSS falls, the clock is validated on the serializer, which processes the number of bits
defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed
following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the
SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no
effect when the SPI is programmed in Slave Mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
When all the bits are processed, the received data is transferred in the Receive Data Register
and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before
new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is
set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES
bit.
When a transfer starts, the data shifted out is the data present in the Shift Register. If no data
has been written in the Transmit Data Register (SPI_TDR), the last data received is trans-
ferred. If no data has been received since the last reset, all bits are transmitted low, as the
Shift Register resets at 0.
When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and
the TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e.
NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data
written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables
frequent updates of critical variables with single transfers.
Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no
character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the
last load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last
received character is retransmitted.
Figure 33-9 shows a block diagram of the SPI when operating in Slave Mode.