Rainbow Electronics AT91CAP9S250A - Manual (Page 171)

171
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
22.6 External Memory Mapping
The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address
up to 64 Mbytes of memory.
If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps
around and appears to be repeated within this space. The SMC correctly handles any valid
access to the memory device within the page (see
Figure 22-2 ).
A[25:0] is only significant for 8-bit memory, A[25:1] is used for 16-bit memory, A[25:2] is used for
32-bit memory.
Figure 22-2. Memory Connections for Eight External Devices
22.7 Connection to External Devices
22.7.1 Data Bus Width
A data bus width of 8, 16, or 32 bits can be selected for each chip select. This option is con-
trolled by the field DBW in SMC_MODE (Mode Register) for the corresponding chip select.
Figure 22-3 shows how to connect a 512K x 8-bit memory on NCS2. Figure 22-4 shows how to
connect a 512K x 16-bit memory on NCS2. Figure 22-5 shows two 16-bit memories connected
as a single 32-bit memory
22.7.2 Byte Write or Byte Select Access
Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of
write access: byte write or byte select access. This is controlled by the BAT field of the
SMC_MODE register for the corresponding chip select.
NRD
NWE
A[25:0]
D[31:0]
8 or 16 or 32
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Output Enable
Write Enable
A[25:0]
D[31:0] or D[15:0] or
D[7:0]
NCS3
NCS0
NCS1
NCS2
NCS7
NCS4
NCS5
NCS6
NCS[0] - NCS[7]
SMC