Rainbow Electronics AT91CAP9S250A - Manual (Page 249)

249
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
parameters, additional clock cycles are inserted to check programmed latency. A single access
owait signal is monitored, or not, in function of the Cellular Ram version.
Write accesses to the Cellular Ram are burst oriented, the programmed burst length is continu-
ous burst. This feature makes it possible to start at a specified address and burst through the
entire memory. It is very useful for incrementing bursts (INCR/INCR4/INCR8/INCR16), as soon
as the burst command init (latch burst start address) is initiated and latency is checked, at each
BCCK rising a data is written.
In the case of a wrapping burst (WRAP4/WRAP8/WRAP16), the addresses can cross the
boundary of the current transfer. For example, when a transfer (WRAP4) starts to address 0x0C,
the next access will be 0x00, but the burst length being programmed to continuous burst in the
next access should be 0x10, the burst does not wrap automatically. The BCRAMC takes
account of this feature and in the case of a transfer starting from address 0x04/0x08/0x0C, two
initial burst write commands will be issued to wrap when boundary is reached. The last
initial
burst write command will be interrupted by a BCCS (chip select) set to high or by another initial
burst read/write command to do the next access in the Cellular Ram device, if an access is
pending.
Figure 24-3. Single Write Access, No Refresh Collision
DO D1
Latency = 3
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D[31:0]
BCOE
BCWE
BCOWAIT