Rainbow Electronics AT91CAP9S250A - Manual (Page 159)

159
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
21.6.3 16-bit Mobile DDR
21.6.3.1 Hardware Configuration
21.6.3.2 Software Configuration
The following configuration has to be performed:
• Initialize the SDRAM Controller depending on th DDR device and system bus frequency.
• The Data Bus Width is to be programmed to 16 bits.
• The SDRAM initialization sequence is described in the “DDR-SDRAM device initialisation”
part of the DDRSDR-SDRAM controller.
A10
A11
D4
A13
D2
A8
D10
D5
D12
A6
A3
D9
D14
D15
A14
A16
A17
D3
A9
D0
A5
D6
D7
A2
D8
D1
A4
D13
D11
A7
A0
SDDRCS
SDWE
RAS
SDCKN
DQS0
DQS1
CAS
SDA10
NBS1
SDCK
SDCKE
D[0..15]
A[0..17]
VDDIOM
(NBS0)
(BA0)
(BA1)
C7 100NF C7 100NF
U1 U1
A0
J8
A1
J9
A2
K7
A3
K8
A4
K2
A5
K3
A6
J1
A7
J2
A8
J3
A9
H1
A10
J7
BA0
H8
A12
H3
DQ0
A8
DQ1
B7
DQ2
B8
DQ3
C7
DQ4
C8
DQ5
D7
DQ6
D8
DQ7
E7
DQ8
E3
DQ9
D2
DQ10
D3
DQ11
C2
DQ12
C3
DQ13
B2
DQ14
B3
DQ15
A2
VDD
A9
VSS
A1
VSS
F1
VDDQ
A7
VDD
K9
N.C
F3
CK
G2
CKE
G1
LDM
F8
UDM
F2
CAS
G8
RAS
G9
WE
G7
CS
H7
VDDQ
B1
VDDQ
C9
VDDQ
D1
VSSQ
A3
VSSQ
B9
VSSQ
C1
VSSQ
D9
VDD
F9
VSS
K1
A11
H2
BA1
H9
CK
G3
VDDQ
E9
VSSQ
E1
LDQS
E8
UDQS
E2
N.C
F7
C1 100NF C1 100NF
C4 100NF C4 100NF
C2 100NF C2 100NF
C3 100NF
C3 100NF
C5 100NF C5 100NF
C8 100NF C8 100NF
C6 100NF C6 100NF