Rainbow Electronics AT91CAP9S250A User Manual
Page 624
624
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
37.6.2.1
AC97 Controller Setup
The following operations must be performed in order to bring the AC’97 Controller into an
operating state:
1.
Enable the AC97 Controller clock in the PMC controller.
2.
Turn on AC97 function by enabling the ENA bit in AC97 Controller Mode Register
(AC97C_MR).
3.
Configure the input channel assignment by controlling the AC’97 Controller Input
Assignment Register (AC97C_ICA).
4.
Configure the output channel assignment by controlling the AC’97 Controller Input
Assignment Register (AC97C_OCA).
5.
Configure sample width for Channel A and Channel B by writing the SIZE bit field in
AC97C Channel A Mode Register (AC97C_CAMR) and AC97C Channel B Mode
Register (AC97C_CBMR). The application can write 10, 16, 18,or 20-bit wide PCM
samples through the AC’97 interface and they will be transferred into 20-bit wide
slots.
6.
Configure data Endianness for Channel A and Channel B by writing CEM bit field in
AC97C_CAMR and AC97C_CBMR registers. Data on the AC-link are shifted MSB
first. The application can write little- or big-endian data to the AC’97 Controller
interface.
7.
Configure the PIO controller to drive the RESET signal of the external Codec. The
RESET signal must fulfill external AC97 Codec timing requirements.
8.
Enable Channel A and/or Channel B by writing CEN bit field in AC97C_CAMR and
AC97C_CBMR registers.
37.6.2.2
Transmit Operation
The application must perform the following steps in order to send data via a channel to the
AC97 Codec:
• Check if previous data has been sent by polling TXRDY flag in the AC97C Channel x
Status Register (AC97_CxSR). x being one of the 3 channels.
• Write data to the AC’97 Controller Channel x Transmit Holding Register (AC97C_CxTHR).
Once data has been transferred to the Channel x Shift Register, the TXRDY flag is automati-
cally set by the AC’97 Controller which allows the application to start a new write action. The
application can also wait for an interrupt notice associated with TXRDY in order to send data.
The interrupt remains active until TXRDY flag is cleared..