Rainbow Electronics AT91CAP9S250A - Manual (Page 769)

769
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
41.8.3 Write Operation
In write operation, the MCI Mode Register (MCI_MR) is used to define the padding value when
writing non-multiple block size. If the bit PDCPADV is 0, then 0x00 value is used when pad-
ding data, otherwise 0xFF is used.
If set, the bit PDCMODE enables PDC transfer.
The following flowchart shows how to write a single block with or without use of PDC facilities
(see
Figure 41-9 ). Polling or interrupt method can be used to wait for the end of write accord-
ing to the contents of the Interrupt Mask Register (MCI_IMR).