Rainbow Electronics AT91CAP9S250A - Manual (Page 764)

764
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Card addressing is implemented using a session address assigned during the initialization
phase by the bus controller to all currently connected cards. Their unique CID number identi-
fies individual cards.
The structure of commands, responses and data blocks is described in the MultiMedia-Card
System Specification. See also
Table 41-4 on page 765 .
MultiMediaCard bus data transfers are composed of these tokens.
There are different types of operations. Addressed operations always contain a command and
a response token. In addition, some operations have a data token; the others transfer their
information directly within the command or response structure. In this case, no data token is
present in an operation. The bits on the DAT and the CMD lines are transferred synchronous
to the clock MCI Clock.
Two types of data transfer commands are defined:
• Sequential commands: These commands initiate a continuous data stream. They are
terminated only when a stop command follows on the CMD line. This mode reduces the
command overhead to an absolute minimum.
• Block-oriented commands: These commands send a data block succeeded by CRC bits.
Both read and write operations allow either single or multiple block transmission. A multiple
block transmission is terminated when a stop command follows on the CMD line similarly to
the sequential read or when a multiple block transmission has a pre-defined block count (
See
“Data Transfer Operation” on page 766. ).
The MCI provides a set of registers to perform the entire range of MultiMedia Card operations.
41.7.1 Command - Response Operation
After reset, the MCI is disabled and becomes valid after setting the MCIEN bit in the MCI_CR
Control Register.
The PWSEN bit saves power by dividing the MCI clock by 2 PWSDIV + 1 when the bus is
inactive.
The two bits, RDPROOF and WRPROOF in the MCI Mode Register (MCI_MR) allow stopping
the MCI Clock during read or write access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
The command and the response of the card are clocked out with the rising edge of the MCI
Clock.
All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification.
The two bus modes (open drain and push/pull) needed to process all the operations are
defined in the MCI command register. The MCI_CMDR allows a command to be carried out.
For example, to perform an ALL_SEND_CID command:
41.8
Host Command N
ID
Cycles CID
CMD S T Content CRC E Z ****** Z S T Content Z Z Z