Rainbow Electronics AT91CAP9S250A - Manual (Page 66)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Table 8 gives an overview of the supported transfers and different kinds of transactions they are
used for.
12.8.2 Thumb Instruction Fetches
All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses
on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time.
12.8.3 Address Alignment
The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the
necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses
are aligned to word boundaries.
Table 12-7. Supported Transfers
HBurst[2:0] Description
SINGLE Single transfer
Single transfer of word, half word, or byte:
• data write (NCNB, NCB, WT, or WB that has missed in DCache)
• data read (NCNB or NCB)
• NC instruction fetch (prefetched and non-prefetched)
• page table walk read
INCR4 Four-word incrementing burst
Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB,
NCB, WT, or WB write.
INCR8 Eight-word incrementing burst Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write.
WRAP8 Eight-word wrapping burst Cache linefill