Rainbow Electronics AT91CAP9S250A - Manual (Page 3)

3
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
• One AC97 Controller (AC97C)
– 6-channel Single AC97 Analog Front End Interface, Slot Assigner
• Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA ® Infrared Modulation/Demodulation, Manchester
Encoding/Decoding
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
• Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Synchronous Communications at Up to 90 Mbits/sec
• One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• One Four-channel 16-bit PWM Controller (PWMC)
• One Two-wire Interface (TWI)
– Master and Slave Mode Support, All Two-wire Atmel EEPROMs Supported
• IEEE ® 1149.1 JTAG Boundary Scan on All Digital Pins
• Required Power Supplies:
– 1.08V to 1.32V for VDDCORE and VDDBU
– 3.0V to 3.6V for VDDOSC, VDDPLL and VDDIOP0 (Peripheral I/Os)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOP1 (Peripheral I/Os) and for VDDIOM
(Memory I/Os) and VDDIOMPP/VDDIOMP (MP Block I/Os)
• Available in 324- and 400-ball LFBGA RoHS-compliant Packages
1. Description
The AT91CAP9S500A/AT91CAP9S250A family is based on the integration of an ARM926EJ-S
processor with fast ROM and SRAM memories, and a wide range of peripherals. By providing up
to 500K gates of metal programmable logic, AT91CAP9S500A/AT91CAP9S250A is the ideal
platform for creating custom designs.
The AT91CAP9S500A/AT91CAP9S250A embeds a USB High-speed Device, a 2-port USB
OHCI Host, an LCD Controller, a 4-channel DMA Controller, and one Image Sensor Interface. It
also integrates several standard peripherals, such as USART, SPI, TWI, Timer Counters, PWM
generators, Multimedia Card interface, and one CAN Controller.
The AT91CAP9S500A/AT91CAP9S250A is architectured on a 12-layer matrix, allowing a maxi-
mum internal bandwidth of twelve 32-bit buses. It also features one external memory bus (EBI)
capable of interfacing with a wide range of memory devices.
The initial release of the AT91CAP9S500A/AT91CAP9S250A is packaged in a 400-ball LFBGA
RoHS-compliant package. A future release will also be available in a 324-ball LFBGA RoHS-
compliant package.