Motorola ColdFire MCF5281 - Manual (Page 762)

Index-14 Freescale Semiconductor
test data input/development serial input (TDI/DSI) 31-3
test data output/development serial output
(TDO/DSO) 31-4
test mode select/breakpoint (TMS/BKPT) 31-3
test reset/development serial clock
(TRST/DSCLK) 31-3
overview 14-1
power and reference
V
DD
14-32
V
DDA
, V
SSA
14-32
V
DDF
, V
SSF
14-32
V
DDH
14-32
V
DDPLL
, V
SSPLL
14-32
V
PP
14-32
V
RH
,
VRL
14-32
V
SS
14-32
V
STBY
14-32
QADC
analog input (ANn/ANx) 14-28 – 14-29
analog power (V
DDA
, V
SSA)
28-56
analog reference (V
RH
, V
RL
) 28-56
dedicated digital I/O port supply (V
DDH
) 28-6
external trigger input (ETRIG2–1) 28-5
multiplexed address output (MA1–0) 28-5
multiplexed analog input (ANx) 28-5
port QA analog input (AN56–55, 53–52) 28-4
port QA digital input/output (PQA4–3, 1–0) 28-4
port QB analog input (AN3–0) 28-4
port QB digital I/O (PQB3–0) 28-5
QSPI
chip select (QSPI_CS3–0) 14-25
serial clock (QSPI_CLK) 14-25
summary 22-2
synchronous serial data input (QSPI_DIN) 14-25
synchronous serial data output (QSPI_DOUT) 14-25
reset controller
reset in (RSTI) 14-22 , 29-2
reset out (RSTO) 29-2
SDRAM controller
bank select (SDRAM_CS1–0) 14-21
clock enable (SCKE) 14-22
column address strobe (SCAS) 14-21
row address strobe (SRAS) 14-21
summary 15-4
write enable (DRAMW) 14-21
single-chip mode 14-17
TEST 14-31
UART modules
clear-to-send (UCTS1–0) 14-26
receive serial data input (URXD2–0) 14-26
request-to-send (URTS1–0) 14-27
transmit serial data output (UTXD2–0) 14-26
SRAM
cache, interaction 4-7
features 5-1
initialization 5-3
operation
low-power modes 7-6
overview 5-1
power management 5-4
programming model 5-1
timing diagrams
bus cycle terminated by TA 33-15
bus cycle terminated by TEA 33-16
Stack pointer 2-5
Stack pointer registers
BDM accesses 30-33
Start-of-frame (SOF) 25-13
STOP instruction 30-4
, 30-17
Stop mode 7-6
STUFFERR 25-26
System clock
generation 9-11
modes 9-10
T
TAP controller 31-6
TEST_LEAKAGE 31-8
Time quanta clock 25-12
Time stamp 25-6
, 25-12
Timer overflow interrupt 20-22
Timers
DTIM
capture mode 21-8
code example 21-9
operation
general 21-9
output mode 21-9
prescaler 21-8
reference compare 21-8
registers
capture (DTCRn) 21-7
counters (DTCNn) 21-8
event (DTERn) 21-5
mode (DTMRn) 21-3
reference (DTRRn) 21-7
time-out values 21-10
general purpose, see general purpose timers
PIT
block diagram 19-1
interrupts 19-7
memory map 19-2
operation
free-running 19-6
low-power modes 19-1
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3