Toshiba H1 SERIES TLCS-900 - Manual (Page 10)

TMP92CM22
2007-02-16 92CM22-8
3.1.2 Reset Operation
When resetting the TMP92CM22 microcontroller, ensure that the power supply voltage
is within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then hold the RESET input to low for at least 20 system clocks (16
μs at fc = 40
MHz).
When the reset has been accepted, the CPU performs the following:
• Sets the program counter (PC) as follows in accordance with the reset vector stored
at address FFFF00H to FFFF02H:
PC<7:0> ← Data in location FFFF00H
PC<15:8> ← Data in location FFFF01H
PC<23:16> ← Data in location FFFF02H
• Sets the stack pointer (XSP) to 00000000H.
• Sets bits <IFF0:2> of the status register (SR) to 111 (Thereby setting the interrupt
level mask register to level 7).
• Clears bits <RFP0:1> of the status register to 00 (Thereby selecting register bank
0).
When the reset is released, the CPU starts executing instructions according to the
program counter settings. CPU internal registers not mentioned above do not change when
the reset is released.
When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
• Initializes the internal I/O registers as “Table of Special Function Registers
(SFRs)” in Section 5.
• Sets the input or output port to general-purpose input port.
Internal reset is released as soon as external reset is released and RESET input pin is set to “H”.
The operation of memory controller cannot be insured until power supply becomes stable after power-on reset. The
external RAM data provided before turning on the TMP92CM22 may be spoiled because the control signals are
unstable until power supply becomes stable after power on reset.
Figure 3.1.1 shows the timing of a reset for the TMP92CM22.