Toshiba H1 SERIES TLCS-900 - Manual (Page 80)

TMP92CM22
2007-02-16 92CM22-78
3.6 Memory Controller
3.6.1 Function
TMP92CM22 has a memory controller with a variable 4-block address area that controls
as follows.
(1) 4-block address area support
Specifies a start address and a block size for 4-block address area.
(2) Connecting memory specifications
Specifies SRAM and ROM as memories to connect with the selected address areas.
(3) Data bus size selection
Whether 8-bit or 16-bit is selected as the data bus size of the respective block address
areas.
(4) Wait control
Wait specification bit in the control register and WAIT input pin control the number of
waits in the external bus cycle. Read cycle and write cycle can specify the number of
waits individually.
The number of waits is controlled in 6 mode mentioned below.
0 waits, 1 wait,
2 waits, 3 waits, 4 waits
N waits (Control with WAIT pin)