Toshiba H1 SERIES TLCS-900 - Manual (Page 103)

TMP92CM22
2007-02-16 92CM22-101
Figure 3.7.2 TMRA23 Block Diagram
φT1
φT16
φT256
8-bit comparato
r
register (CP3
)
8-bit comparato
r
(CP2)
8-bit up counter
(UC2
)
2
n
over- flow
8-bit up counter
(UC3
)
Ti
mer
flip-
flop
TA3FF
Match detect
Match detect
8-bit timer
register TA3RE
G
φT1 φT4
φT16
512
256
128
64
32
16
8
4
2
φT1
φT4
φT16
φT256
Run/clea
r
Pr
escale
r
TA23MOD <TA2CLK1:0>
Pr
escale
r
clock:
φT0
TA23RU
N
<TA2
RUN>
Selecto
r
8-bit timer regist
er
TA2REG
TA23MOD <PWM21:20>
TA23MOD <TA23M1:0>
TMRA2 interrupt out
put:
INTTA2
TMRA2 match output: TA2TR
G
TA23MOD <TA3CLK1:0>
TA23RU
N<TA3
RUN>
TA3FF
CR
Ti
mer fl
ip
-fl
op
output: T
A
3
O
U
T
TMRA3 interrupt out
ptu:
INTTA3
Internal data b
u
s
TA23RU
N
<TA2RDE>
TA23RU
N
<TA23PRUN>
Selecto
r
Internal data b
u
s
TA2TR
G
Register buffer
2