Toshiba H1 SERIES TLCS-900 - Manual (Page 214)

TMP92CM22
2007-02-16 92CM22-212
3.12.2 Operation
The watchdog timer generates an INTWD interrupt when the detection time set in the
WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared “0” in software
before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway
occurs) due to causes such as noise, but does not execute the instruction used to clear the
binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
The CPU will detect malfunction (runaway) due to the INTWD interrupt and in this case it
is possible to return to the CPU to normal operation by means of an anti-malfunction
program.
The watchdog timer begins operating immediately on release of the watchdog timer
reset.
The watchdog timer is halted in IDLE1 or STOP mode. The watchdog timer counter
continues counting during bus release (when BUSAK goes low).
When the device is in IDLE2 mode, the operation of WDT depends on the
WDMOD<I2WDT> setting. Ensure that WDMOD<I2WDT> is set before the device enters
IDLE2 mode.
The watchdog timer consists of a 22-stage binary counter which uses the clock φ (2/f
IO
) as
the input clock. The binary counter can output 2 15 /f
IO
, 2 17 /f
IO
, 2 19 /f
IO
and 2 21 /f
IO
.
Figure 3.12.2 Normal Mode
The runaway detection result can also be connected to the reset pin internally.
In this case, the reset time will be between 22 and 29 system clocks (35.2 to 46.4 μs at
f
OSCH
= 40 MHz) as shown inFigure 3.12.3. After a reset, the f
SYS
clock is f
FPH
/2, where
f
FPH
is generated by dividing the high-speed oscillator clock (f
OSCH
) by sixteen through the
clock gear function
Figure 3.12.3 Reset Mode
Overflow n 0 WDT counter
WDT interrupt
WDT clear
(Software)
Write clear code
n WDT counter
WDT interrupt
22 to 29 clocks (35.2 to 46.4
μs at f
OSCH
= 40 MHz)
Overflow
Internal reset