Toshiba H1 SERIES TLCS-900 - Manual (Page 50)

TMP92CM22
2007-02-16 92CM22-48
(7) Notes
The instruction execution unit and the bus interface unit in this CPU operate
independently. Therefore if, immediately before an interrupt is generated, the CPU
fetches an instruction which clears the corresponding interrupt request flag (Note), the
CPU may execute this instruction in between accepting the interrupt and reading the
interrupt vector. In this case, the CPU will read the default vector 0004H and jump to
interrupt vector address FFFF04H.
To avoid this, an instruction which clears an interrupt request flag should always be
placed after a DI instruction. And in the case of setting an interrupt enable again by
EI instruction after the execution of clearing instruction, execute EI instruction after
clearing and more than 3-instructions (e.g., “NOP”
× 3 times).
If placed EI instruction without waiting NOP instruction after execution of clearing
instruction, interrupt will be enable before request flag is cleared. Thus, when be
changed interrupt request level to “0”, change it after cleared corresponding interrupt
request by INTCLR instruction.
In the case of changing the value of the interrupt mask register <IFF2:0> by
execution, disable an interrupt by DI instruction before execution of POPSR
instruction.
In addition, please note that the following two circuits are exceptional and demand
special attention.
In level mode INT0 to INT3 are not an edge-triggered interrupt. Hence, in level
mode the interrupt request flip-flop for INT0 to INT3 does not function. The
peripheral interrupt request passes through the S input of the flip-flop and
becomes the Q output. If the interrupt input mode is changed from edge mode
to level mode, the interrupt request flag is cleared automatically.
INT0 to INT3 level mode
If the CPU enters the interrupt response sequence as a result of INT x (x
= 0, 1, 2,
or 3) going from 0 to 1, INTx must then be held at 1 until the interrupt response
sequence has been completed. If INTx is set to Level mode so as to release a
Halt state, INTx must be held at 1 from the time INTx changes from 0 to 1 until the
Halt state is released. (Hence, it is necessary to ensure that input noise is not
interpreted as a 0, causing INTx to revert to 0 before the Halt state has been
released.)
When the mode changes from level mode to edge mode, interrupt request flags
which were set in level mode will not be cleared. Interrupt request flags must be
cleared using the following sequence.
DI
LD (IIMC), 00H ; Changes from level to edge.
LD (INTCLR), 0AH ; Clears interrupt request flag.
NOP ; Wait EI execution.
NOP
NOP
EI
INTRX
The interrupt request flip-flop can only be cleared by a reset or by reading the
serial channel receive buffer. It cannot be cleared by writing INTCLR register.
Note: The following instructions or pin input state changes are equivalent to instructions
that clear the interrupt request flag.
INT0 to INT 3: Instructions which switch to level mode after an interrupt request has
been generated in edge mode.
The pin input change from high to low after interrupt request has
been generated in level mode. (“H”
→ “L”, “L” →“H”)
INTRX: Instruction which read the receive buffer.