Rainbow Electronics ATmega128L - Manual (Page 107)

107
ATmega128(L)
2467B–09/01
Figure 45. 16-bit Timer/Counter Block Diagram
Note: Refer to Figure 1 on page 2, Table 30 on page 69, and Table 39 on page 76 for
Timer/Counter1 and 3 pin placement and description.
Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Cap-
ture Register (ICRn) are all 16-bit registers. Special procedures must be followed when
accessing the 16-bit registers. These procedures are described in the section
“Access-
ing 16-bit Registers” on page 109. The Timer/Counter Control Registers (TCCRnA/B/C)
are 8-bit registers and have no CPU access restrictions. Interrupt requests (shorten as
Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR) and Extended
Timer Interrupt Flag Register (ETIFR). All interrupts are individually masked with the
Timer Interrupt Mask register (TIMSK) and Extended Timer Interrupt Mask register
(ETIMSK). (E)TIFR and (E)TIMSK are not shown in the figure since these registers are
shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock
source on the Tn pin. The Clock Select logic block controls which clock source and edge
the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is
inactive when no clock source is selected. The output from the clock select logic is
referred to as the timer clock (clk
T n
).
ICFx (Int.Req.)
TOVx
(Int.Req.)
Clock Select
Timer/Counter
DATABUS
OCRxA
OCRxB
OCRxC
ICRx
=
=
=
TCNTx
Waveform
Generation
Waveform
Generation
Waveform
Generation
OCxA
OCxB
OCxC
Noise
Canceler
ICPx
=
Fixed
TOP
Values
Edge
Detector
Control Logic
= 0
TOP BOTTOM
Count
Clear
Direction
OCFxA
(Int.Req.)
OCFxB
(Int.Req.)
OCFxC
(Int.Req.)
TCCRxA TCCRxB TCCRxC
( From Analog
Comparator Ouput )
Tx
Edge
Detector
( From Prescaler )
TCLK