Rainbow Electronics ATmega128L - Manual (Page 198)

198
ATmega128(L)
2467B–09/01
• Bits 7..0 - TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a
frequency divider which generates the SCL clock frequency in the master modes. See
“Bit Rate Generator Unit” on page 196 for calculating bit rates.
TWI Control Register – TWCR
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to
initiate a master access by applying a START condition to the bus, to generate a
receiver acknowledge, to generate a stop condition, and to control halting of the bus
while the data to be written to the bus are written to the TWDR. It also indicates a write
collision if data is attempted written to TWDR while the register is inaccessible.
• Bit 7 - TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects appli-
cation software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will
jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is
stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note
that this flag is not automatically cleared by hardware when executing the interrupt rou-
tine. Also note that clearing this flag starts the operation of the TWI, so all accesses to
the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Regis-
ter (TWDR) must be complete before clearing this flag.
• Bit 6 - TWEA: TWI Enable Acknowledge Bit
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is writ-
ten to one, the ACK pulse is generated on the TWI bus if the following conditions are
met:
1. The device’s own slave address has been received.
2. A general call has been received, while the TWGCE bit in the TWAR is set.
3. A data byte has been received in master receiver or slave receiver mode.
By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire
Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA
bit to one again.
• Bit 5 - TWSTA: TWI START Condition Bit
The application writes the TWSTA bit to one when it desires to become a master on the
2-wire Serial Bus. The TWI hardware checks if the bus is available, and generates a
START condition on the bus if it is free. However, if the bus is not free, the TWI waits
until a STOP condition is detected, and then generates a new START condition to claim
the bus Master status. TWSTA is cleared by the TWI hardware when the START condi-
tion has been transmitted.
• Bit 4 - TWSTO: TWI STOP Condition Bit
Writing the TWSTO bit to one in master mode will generate a STOP condition on the 2-
wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is
cleared automatically. In slave mode, setting the TWSTO bit can be used to recover
from an error condition. This will not generate a STOP condition, but the TWI returns to
a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high
impedance state.
Bit 7 6 5 4 3 2 1 0
TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE TWCR
Read/Write R/W R/W R/W R/W R R/W R R/W
Initial value 0 0 0 0 0 0 0 0