Rainbow Electronics ATmega128L - Manual (Page 149)

149
ATmega128(L)
2467B–09/01
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR2 register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to
BOTTOM, the output will be continuously low and if set equal to MAX the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values.
Timer/Counter Timing
Diagrams The Timer/Counter is a synchronous design and the timer clock (clk
T2
) is therefore
shown as a clock enable signal in the following figures. The figures include information
on when interrupt flags are set.
Figure 67 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.
Figure 67. Timer/Counter Timing Diagram, no Prescaling
Figure 68 shows the same timing data, but with the prescaler enabled.
Figure 68. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
Figure 69 shows the setting of OCF2 in all modes except CTC mode.
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)