Rainbow Electronics ATmega128L - Manual (Page 99)

99
ATmega128(L)
2467B–09/01
Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-
initions. However, the functionality and location of these bits are compatible with
previous versions of the timer.
• Bit 5:4 - COM01:0: Compare Match Output Mode
These bits control the output compare pin (OC0) behavior. If one or both of the
COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-
sponding to OC0 pin must be set in order to enable the output driver.
When OC0 is connected to the pin, the function of the COM01:0 bits depends on the
WGM01:0 bit setting.
Table 53 shows the COM01:0 bit functionality when the WGM01:0
bits are set to a normal or CTC mode (non-PWM).
Table 54 shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast
PWM mode.
Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the
compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode”
on page 93 for more details.
Table 55 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase
correct PWM mode.
Table 52. Waveform Generation Mode Bit Description
Mode
WGM01 (1)
(CTC0)
WGM00 (1)
(PWM0)
Timer/Counter
Mode of Operation
TOP
Update of
OCR0 at TOV0 Flag
Set on
0 0 0 Normal 0xFF Immediate MAX
1 0 1 PWM, Phase
Correct 0xFF TOP BOTTOM
2 1 0 CTC OCR0 Immediate MAX
3 1 1 Fast PWM 0xFF TOP MAX
Table 53. Compare Output Mode, Non-PWM Mode
COM01 COM00 Description
0 0 Normal port operation, OC0 disconnected.
0 1 Toggle OC0 on compare match
1 0 Clear OC0 on compare match
1 1 Set OC0 on compare match
Table 54. Compare Output Mode, Fast PWM Mode (1)
COM01 COM00 Description
0 0 Normal port operation, OC 0 disconnected.
0 1 Reserved
1 0 Clear OC 0 on compare match, set OC0 at TOP
1 1 Set OC 0 on compare match, clear OC0 at TOP