Rainbow Electronics ATmega128L - Manual (Page 174)

174
ATmega128(L)
2467B–09/01
interrupt-driven data transmission is used, the data register empty Interrupt routine must
either write new data to UDR in order to clear UDRE or disable the data register empty
interrupt, otherwise a new interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXC) flag bit is set one when the entire frame in the transmit
shift register has been shifted out and there are no new data currently present in the
transmit buffer. The TXC flag bit is automatically cleared when a transmit complete inter-
rupt is executed, or it can be cleared by writing a one to its bit location. The TXC flag is
useful in half-duplex communication interfaces (like the RS485 standard), where a
transmitting application must enter receive mode and free the communication bus
immediately after completing the transmission.
When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART
Transmit Complete Interrupt will be executed when the TXC flag becomes set (provided
that global interrupts are enabled). When the transmit complete interrupt is used, the
interrupt handling routine does not have to clear the TXC flag, this is done automatically
when the interrupt is executed.
Parity Generator The parity generator calculates the parity bit for the serial frame data. When parity bit is
enabled (UPM1 = 1), the transmitter control logic inserts the parity bit between the last
data bit and the first stop bit of the frame that is sent.
Disabling the Transmitter The disabling of the transmitter (setting the TXEN to zero) will not become effective until
ongoing and pending transmissions are completed, i.e. when the transmit shift register
and transmit buffer register do not contain data to be transmitted. When disabled, the
transmitter will no longer override the TxD pin.
Data Reception – The
USART Receiver The USART receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB
register to one. When the receiver is enabled, the normal pin operation of the RxD pin is
overridden by the USART and given the function as the receiver’s serial input. The baud
rate, mode of operation and frame format must be set up once before any serial recep-
tion can be done. If synchronous operation is used, the clock on the XCK pin will be
used as transfer clock.
Receiving Frames with 5 to 8
Data Bits The receiver starts data reception when it detects a valid start bit. Each bit that follows
the start bit will be sampled at the baud rate or XCK clock, and shifted into the receive
shift register until the first stop bit of a frame is received. A second stop bit will be
ignored by the receiver. When the first stop bit is received, i.e. a complete serial frame is
present in the receive shift register, the contents of the shift register will be moved into
the receive buffer. The receive buffer can then be read by reading the UDR I/O location.