Rainbow Electronics ATmega128L - Manual (Page 95)

95
ATmega128(L)
2467B–09/01
Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 3) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-
slope operation. The counter counts repeatedly from BOTTOM to MAX and then from
MAX to BOTTOM. In non-inverting compare output mode, the output compare (OC0) is
cleared on the compare match between TCNT0 and OCR0 while upcounting, and set on
the compare match while downcounting. In inverting output compare mode, the opera-
tion is inverted. The dual-slope operation has lower maximum operation frequency than
single slope operation. However, due to the symmetric feature of the dual-slope PWM
modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to 8 bits. In phase correct
PWM mode the counter is incremented until the counter value matches Max When the
counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to
MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is
shown on
Figure 39. The TCNT0 value is in the timing diagram shown as a histogram
for illustrating the dual-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare
matches between OCR0 and TCNT0.
Figure 39. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter overflow flag ( TOV0 ) is set each time the counter reaches BOTTOM.
The interrupt flag can be used to generate an interrupt each time the counter reaches
the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on
the OC0 pin. Setting the COM01:0 bits to 2 will produce a non-inverted PWM. An
inverted PWM output can be generated by setting the COM01:0 to 3 (See
Table 55 on
page 100). The actual OC0 value will only be visible on the port pin if the data direction
for the port pin is set as output. The PWM waveform is generated by clearing (or setting)
the OC0 register at the compare match between OCR0 and TCNT0 when the counter
increments, and setting (or clearing) the OC0 register at compare match between OCR0
TOVn Interrupt Flag Set
OCn Interrupt Flag Set
1 2 3
TCNTn
Period
OCn
OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
OCRn Update