Rainbow Electronics ATmega128L - Manual (Page 210)

210
ATmega128(L)
2467B–09/01
Slave Receiver Mode In the slave receiver mode, a number of data bytes are received from a master transmit-
ter (see
Figure 99). All the status codes mentioned in this chapter assume that the
prescaler bits are zero or are masked to zero.
Figure 99. Data Transfer in Slave Receiver Mode
To initiate the slave receiver mode, TWAR and TWCR must be initialized as follows:
The upper 7 bits are the address to which the 2-wire Serial Interface will respond when
addressed by a master. If the LSB is set, the TWI will respond to the general call
address ($00), otherwise it will ignore the general call address.
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one
to enable the acknowledgment of the device’s own slave address or the general call
address. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its
own slave address (or the general call address if enabled) followed by the data direction
bit. If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode
is entered. After its own slave address and the write bit have been received, the TWINT
flag is set and a valid status code can be read from TWSR. The status code is used to
determine the appropriate software action. The appropriate action to be taken for each
status code is detailed in
Table 89. The slave receiver mode may also be entered if arbi-
tration is lost while the TWI is in the master mode (see states $68 and $78).
If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”)
to SDA after the next received data byte. This can be used to indicate that the slave is
not able to receive any more bytes. While TWEA is zero, the TWI does not acknowledge
its own slave address. However, the 2-wire Serial Bus is still monitored and address rec-
ognition may resume at any time by setting TWEA. This implies that the TWEA bit may
be used to temporarily isolate the TWI from the 2-wire Serial Bus.
In all sleep modes other than Idle Mode, the clock system to the TWI is turned off. If the
TWEA bit is set, the interface can still acknowledge its own slave address or the general
call address by using the 2-wire Serial Bus clock as a clock source. The part will then
wake up from sleep and the TWI will hold the SCL clock low during the wake up and
until the TWINT flag is cleared (by writing it to one). Further data reception will be car-
ried out as normal, with the AVR clocks running as normal. Observe that if the AVR is
TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
value Device’s own slave address
TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE
value 0 1 0 0 0 1 0 X
Device 3 Device n
SDA
SCL
........ R1 R2
V
CC
Device 2
MASTER
TRANSMITTER
Device 1
SLAVE
RECEIVER