Rainbow Electronics ATmega128L - Manual (Page 96)

96
ATmega128(L)
2467B–09/01
and TCNT0 when the counter decrements. The PWM frequency for the output when
using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR0 register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR0 is set equal to
BOTTOM, the output will be continuously low and if set equal to MAX the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values.
Timer/Counter Timing
Diagrams Figure 40 and Figure 41 contain timing data for the Timer/Counter operation. The
Timer/Counter is a synchronous design and the timer clock (clk
T0
) is therefore shown as
a clock enable signal. The figure shows the count sequence close to the MAX value.
Figure 42 and Figure 43 show the same timing data, but with the prescaler enabled. The
figures illustrate when interrupt flags are set.
The following figures show the Timer/Counter in synchronous mode, and the timer clock
(clk
T0
) is therefore shown as a clock enable signal. In asynchronous mode, clk
I/O
should
be replaced by the Timer/Counter Oscillator clock. The figures include information on
when interrupt flags are set.
Figure 40 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.
Figure 40. Timer/Counter Timing Diagram, No Prescaling
Figure 41 shows the same timing data, but with the prescaler enabled.
f
O Cn PCPW M
f
clk_I/O
N
510 ⋅
------------------ =
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1