Rainbow Electronics ATmega128L - Manual (Page 319)

319
ATmega128(L)
2467B–09/01
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
12 t
RLRH
RD Pulse Width TBD 1.0t
CLCL
-TBD ns
13 t
DVWL
Data Setup to WR Low TBD 0.5t
CLCL
-TBD ns
14 t
WHDX
Data Hold After WR High TBD 0.5t
CLCL
-TBD ns
15 t
DVWH
Data Valid to WR High TBD 1.0t
CLCL
-TBD ns
16 t
WLWH
WR Pulse Width TBD 1.0t
CLCL
-TBD ns
Table 142. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state (Continued)
Symbol Parameter
4 MHz Oscillator Variable Oscillator
Unit Min Max Min Max
Table 143. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1
Symbol Parameter
4 MHz Oscillator Variable Oscillator
Unit Min Max Min Max
0 1/t
CLCL
Oscillator Frequency 0.0 TBD MHz
10 t
RLDV
Read Low to Data Valid TBD 2.0t
CLCL
-TBD ns
12 t
RLRH
RD Pulse Width TBD 2.0t
CLCL
-TBD ns
15 t
DVWH
Data Valid to WR High TBD 2.0t
CLCL
-TBD ns
16 t
WLWH
WR Pulse Width TBD 2.0t
CLCL
-TBD ns
Table 144. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
Symbol Parameter
4 MHz Oscillator Variable Oscillator
Unit Min Max Min Max
0 1/t
CLCL
Oscillator Frequency 0.0 TBD MHz
10 t
RLDV
Read Low to Data Valid TBD 3.0t
CLCL
-TBD ns
12 t
RLRH
RD Pulse Width TBD 3.0t
CLCL
-TBD ns
15 t
DVWH
Data Valid to WR High TBD 3.0t
CLCL
-TBD ns
16 t
WLWH
WR Pulse Width TBD 3.0t
CLCL
-TBD ns
Table 145. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
Symbol Parameter
4 MHz Oscillator Variable Oscillator
Unit Min Max Min Max
0 1/t
CLCL
Oscillator Frequency 0.0 TBD MHz
10 t
RLDV
Read Low to Data Valid TBD 3.0t
CLCL
-TBD ns
12 t
RLRH
RD Pulse Width TBD 3.0t
CLCL
-TBD ns
14 t
WHDX
Data Hold After WR High TBD 1.5t
CLCL
-TBD ns
15 t
DVWH
Data Valid to WR High TBD 3.0t
CLCL
-TBD ns
16 t
WLWH
WR Pulse Width TBD 3.0t
CLCL
-TBD ns