Rainbow Electronics ATmega128L - Manual (Page 197)

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ATmega128(L)
2467B–09/01
TWI Control Register (TWCR). When in transmitter mode, the value of the received
(N)ACK bit can be determined by the value in the TWSR.
The START/STOP Controller is responsible for generation and detection of START,
REPEATED START, and STOP conditions. The START/STOP controller is able to
detect START and STOP conditions even when the AVR MCU is in one of the sleep
modes, enabling the MCU to wake up if addressed by a master.
If the TWI has initiated a transmission as master, the Arbitration Detection hardware
continuously monitors the transmission trying to determine if arbitration is in process. If
the TWI has lost an arbitration, the Control Unit is informed. Correct action can then be
taken and appropriate status codes generated.
Address Match Unit The Address Match unit checks if received address bytes match the seven-bit address
in the TWI Address Register (TWAR). If the TWI General Call Recognition Enable
(TWGCE) bit in the TWAR is written to one, all incoming address bits will also be com-
pared against the General Call address. Upon an address match, the Control Unit is
informed, allowing correct action to be taken. The TWI may or may not acknowledge its
address, depending on settings in the TWCR. The Address Match unit is able to com-
pare addresses even when the AVR MCU is in sleep mode, enabling the MCU to wake
up if addressed by a master.
Control Unit The Control unit monitors the TWI bus and generates responses corresponding to set-
tings in the TWI Control Register (TWCR). When an event requiring the attention of the
application occurs on the TWI bus, the TWI interrupt flag (TWINT) is asserted. In the
next clock cycle, the TWI Status Register (TWSR) is updated with a status code identify-
ing the event. The TWSR only contains relevant status information when the TWI
interrupt flag is asserted. At all other times, the TWSR contains a special status code
indicating that no relevant status information is available. As long as the TWINT flag is
set, the SCL line is held low. This allows the application software to complete its tasks
before allowing the TWI transmission to continue.
The TWINT flag is set in the following situations:
• After the TWI has transmitted a START/REPEATED START condition
• After the TWI has transmitted SLA+R/W
• After the TWI has transmitted an address byte
• After the TWI has lost arbitration
• After the TWI has been addressed by own slave address or general call
• After the TWI has received a data byte
• After a STOP or REPEATED START has been received while still addressed as a
slave
• When a bus error has occurred due to an illegal START or STOP condition
TWI Register Description
TWI Bit Rate Register – TWBR
Bit 7 6 5 4 3 2 1 0
TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 TWBR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0