Multi-master systems and arbitration, Atmega128(l) – Rainbow Electronics ATmega128L User Manual
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ATmega128(L)
2467B–09/01
Multi-master Systems
and Arbitration
If multiple masters are connected to the same bus, transmissions may be initiated simul-
taneously by one or more of them. The TWI standard ensures that such situations are
handled in such a way that one of the masters will be allowed to proceed with the trans-
fer, and that no data will be lost in the process. An example of an arbitration situation is
depicted below, where two masters are trying to transmit data to a slave receiver.
Figure 104. An Arbitration Example
Several different scenarios may arise during arbitration, as described below:
•
Two or more masters are performing identical communication with the same slave.
In this case, neither the slave nor any of the masters will know about the bus
contention.
•
Two or more masters are accessing the same slave with different data or direction
bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data
bits. The masters trying to output a one on SDA while another master outputs a zero
will lose the arbitration. Losing masters will switch to not addressed slave mode or
wait until the bus is free and transmit a new START condition, depending on
application software action.
•
Two or more masters are accessing different slaves. In this case, arbitration will
occur in the SLA bits. Masters trying to output a one on SDA while another master
outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to
slave mode to check if they are being addressed by the winning master. If
addressed, they will switch to SR or ST mode, depending on the value of the
READ/WRITE bit. If they are not being addressed, they will switch to not addressed
slave mode or wait until the bus is free and transmit a new START condition,
depending on application software action.
Figure 105. Possible status values are given in circles.
Device 1
MASTER
TRANSMITTER
Device 2
MASTER
TRANSMITTER
Device 3
SLAVE
RECEIVER
Device n
SDA
SCL
........
R1
R2
V
CC