Rainbow Electronics ATmega128L - Manual (Page 138)

138
ATmega128(L)
2467B–09/01
Timer/Counter3,
Timer/Counter2, and
Timer/Counter1
Prescalers
Timer/Counter3, Timer/Counter1, and Timer/Counter0 share the same prescaler mod-
ule, but the timer/counters can have different prescaler settings. The description below
applies to all of the mentioned Timer/Counters.
Internal Clock Source The timer/counter can be clocked directly by the system clock (by setting the CSn2:0 =
1). This provides the fastest operation, with a maximum timer/counter clock frequency
equal to system clock frequency (f
CLK_I/O
). Alternatively, one of four taps from the pres-
caler can be used as a clock source. The prescaled clock has a frequency of either
f
CLK_I/O
/8, f
CLK_I/O
/64, f
CLK_I/O
/256, or f
CLK_I/O
/1024.
Prescaler Reset The prescaler is free running, i.e. operates independently of the clock select logic of the
timer/counter, and it is shared by Timer/Counter1, Timer/Counter2, and Timer/Counter3.
Since the prescaler is not affected by the timer/counter’s clock select, the state of the
prescaler will have implications for situations where a prescaled clock is used. One
example of prescaling artifacts occurs when the timer is enabled and clocked by the
prescaler (6 > CSn2:0 > 1). The number of system clock cycles from when the timer is
enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N
equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the timer/counter to program
execution. However, care must be taken if the other timer/counter that shares the same
prescaler also use prescaling. A prescaler reset will affect the prescaler period for all
timer/counters it is connected to.
External Clock Source An external clock source applied to the Tn pin can be used as timer/counter clock
(clk
T1
/clk
T2
/clk
T3
). The Tn pin is sampled once every system clock cycle by the pin syn-
chronization logic. The synchronized (sampled) signal is then passed through the edge
detector.
Figure 58 shows a functional equivalent block diagram of the Tn synchroniza-
tion and edge detector logic. The registers are clocked at the positive edge of the
internal system clock (
clk
I/O
). The latch is transparent in the high period of the internal
system clock.
The edge detector generates one clk
T1
/clk
T 2
/clk
T 3
pulse for each positive (CSn2:0 = 7) or
negative (CSn2:0 = 6) edge it detects.
Figure 58. Tn Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system
clock cycles from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at
least one system clock cycle, otherwise it is a risk that a false timer/counter clock pulse
is generated.
Tn_sync
(To Clock
Select Logic)
Edge Detector Synchronization
D Q D Q
LE
D Q Tn
clk
I/O