Rainbow Electronics ATmega128L - Manual (Page 148)

148
ATmega128(L)
2467B–09/01
cleared on the compare match between TCNT2 and OCR2 while upcounting, and set on
the compare match while downcounting. In inverting output compare mode, the opera-
tion is inverted. The dual-slope operation has lower maximum operation frequency than
single slope operation. However, due to the symmetric feature of the dual-slope PWM
modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to 8 bits. In phase correct
PWM mode the counter is incremented until the counter value matches Max When the
counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to
MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is
shown on
Figure 66. The TCNT2 value is in the timing diagram shown as a histogram
for illustrating the dual-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare
matches between OCR2 and TCNT2.
Figure 66. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter overflow flag (TOV2) is set each time the counter reaches BOTTOM.
The interrupt flag can be used to generate an interrupt each time the counter reaches
the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on
the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An
inverted PWM output can be generated by setting the COM21:0 to 3 (see
Table 67 on
page 152). The actual OC2 value will only be visible on the port pin if the data direction
for the port pin is set as output. The PWM waveform is generated by clearing (or setting)
the OC2 register at the compare match between OCR2 and TCNT2 when the counter
increments, and setting (or clearing) the OC2 register at compare match between OCR2
and TCNT2 when the counter decrements. The PWM frequency for the output when
using phase correct PWM can be calculated by the following equation:
TOVn Interrupt Flag Set
OCn Interrupt Flag Set
1 2 3
TCNTn
Period
OCn
OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
OCRn Update
f
O Cn PCPW M
f
clk_I/O
N 510 ⋅
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