Rainbow Electronics ATmega128L - Manual (Page 166)

166
ATmega128(L)
2467B–09/01
Figure 78. USART Block Diagram
Note: Refer to Figure 1 on page 2, Table 36 on page 73, and Table 39 on page 76 for USART
pin placement.
The dashed boxes in the block diagram separate the three main parts of the USART
(listed from the top): clock generator, transmitter and receiver. Control registers are
shared by all units. The clock generation logic consists of synchronization logic for exter-
nal clock input used by synchronous slave operation, and the baud rate generator. The
XCK (transfer clock) pin is only used by synchronous transfer mode. The transmitter
consists of a single write buffer, a serial shift register, parity generator and control logic
for handling different serial frame formats. The write buffer allows a continuous transfer
of data without any delay between frames. The receiver is the most complex part of the
USART module due to its clock and data recovery units. The recovery units are used for
asynchronous data reception. In addition to the recovery units, the receiver includes a
parity checker, control logic, a shift register and a two level receive buffer (UDR). The
receiver supports the same frame formats as the transmitter, and can detect frame
error, data overrun and parity errors.
AVR USART vs. AVR UART –
Compatibility The USART is fully compatible with the AVR UART regarding:
• Bit locations inside all USART registers
• Baud Rate Generation
• Transmitter Operation
PARITY
GENERATOR
UBRR[H:L]
UDR (Transmit)
UCSRA UCSRB UCSRC
BAUD RATE GENERATOR
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER RxD
TxD
PIN
CONTROL
UDR (Receive)
PIN
CONTROL
XCK
DATA
RECOVERY
CLOCK
RECOVERY
PIN
CONTROL
TX
CONTROL
RX
CONTROL
PARITY
CHECKER
DATABUS
OSC
SYNC LOGIC
Clock Generator
Transmitter
Receiver