Rainbow Electronics ATmega128L - Manual (Page 63)

63
ATmega128(L)
2467B–09/01
Figure 30. Synchronization when Reading an Externally Applied Pin Value
Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high,
as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is
latched when the system clock goes low. It is clocked into the PINxn register at the suc-
ceeding positive clock edge. As indicated by the two arrows t
pd,max
and t
pd,min
, a single
signal transition on the pin will be delayed between ½ and 1½ system clock period
depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as
indicated in
Figure 31. The out instruction sets the “SYNC LATCH” signal at the positive
edge of the clock. In this case, the delay t
pd
through the synchronizer is 1 system clock
period.
SYSTEM CLK
INSTRUCTIONS
SYNC LATCH
PINxn
r17
in r17, PINx
0xFF 0x00
t
pd, max
XXX XXX
t
pd, min