Rainbow Electronics ATmega128L - Manual (Page 70)

70
ATmega128(L)
2467B–09/01
• OC1B, Bit 6
OC1B, Output Compare matchB output: The PB6 pin can serve as an external output
for the Timer/Counter1 output compareB. The pin has to be configured as an output
(DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM
mode timer function.
• OC1A, Bit 5
OC1A, Output Compare matchA output: The PB5 pin can serve as an external output
for the Timer/Counter1 output compareA. The pin has to be configured as an output
(DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM
mode timer function.
• OC0, Bit 4
OC0, Output Compare match output: The PB4 pin can serve as an external output for
the Timer/Counter0 output compare. The pin has to be configured as an output (DDB4
set (one)) to serve this function. The OC0 pin is also the output pin for the PWM mode
timer function.
• MISO - Port B, Bit 3
MISO: Master data input, slave data output pin for SPI channel. When the SPI is
enabled as a master, this pin is configured as an input regardless of the setting of
DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by
DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB3 bit.
• MOSI - Port B, Bit 2
MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB2.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB2 bit.
• SCK - Port B, Bit 1
SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB1.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB1 bit.
• SS - Port B, Bit 0
SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as
an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin
is driven low. When the SPI is enabled as a master, the data direction of this pin is con-
trolled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled
by the PORTB0 bit.
Table 31 and Table 32 relate the alternate functions of Port B to the overriding signals
shown in
Figure 32 on page 66. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute
the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE
INPUT.