Rainbow Electronics ATmega128L - Manual (Page 27)

27
ATmega128(L)
2467B–09/01
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper
can be disabled and enabled in software as described in
“External Memory Control Reg-
ister B – XMCRB” on page 31. When enabled, the bus-keeper will keep the previous
value on the AD7:0 bus while these lines are tri-stated by the XMEM interface.
If neither bus-keeper nor pull-ups are enabled, the XMEM interface will leave the AD7:0
tri-stated during a read access until the next RAM access (internal or external) appears.
Timing External memory devices have different timing requirements. To meet these require-
ments, the ATmega128 XMEM interface provides four different wait-states as shown in
Table 4. It is important to consider the timing specification of the external memory
device before selecting the wait-state. The most important parameters are the access
time for the external memory compared to the set-up requirement of the ATmega128.
The access time for the external memory is defined to be the time from receiving the
chip select/address until the data of this address actually is driven on the bus. The
access time cannot exceed the time from the ALE pulse must be asserted low until data
is stable during a read sequence (See t
LLRL
+ t
RLRH
- t
DVRH
in Tables 138 through Tables
145 on pages 317 - 319). The different wait-states are set up in software. As an addi-
tional feature, it is possible to divide the external memory space in two sectors with
individual wait-state settings. This makes it possible to connect two different memory
devices with different timing requirements to the same XMEM interface. For XMEM
interface timing details, please refer to
Table 138 to Table 145 and Figure 156 to Figure
159 in the “External Data Memory Timing” on page 317.
Note that the XMEM interface is asynchronous and that the waveforms in the following
figures are related to the internal system clock. The skew between the internal and
external clock (XTAL1) is not guarantied (varies between devices temperature, and sup-
ply voltage). Consequently, the XMEM interface is not suited for synchronous operation.
Figure 13. External Data Memory Cycles without Wait-state
(SRWn1 = 0 and SRWn0 = 0)
(1)
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T4 is only present if the next instruction accesses the RAM
(internal or external).
ALE
T1 T2 T3
Write
Read
WR
T4
A15:8 Address Prev. addr.
DA7:0 Address Data Prev. data XX
RD
DA7:0 (XMBK = 0) Data Prev. data Address
Data Prev. data Address DA7:0 (XMBK = 1)
System Clock (CLK
CPU
)