Usart control and status register c – ucsrc, Atmega128(l) – Rainbow Electronics ATmega128L User Manual
Page 185
185
ATmega128(L)
2467B–09/01
• Bit 1 - RXB8: Receive Data Bit 8
RXB8 is the 9th data bit of the received character when operating with serial frames with
9 data bits. Must be read before reading the low bits from UDR.
• Bit 0 - TXB8: Transmit Data Bit 8
TXB8 is the 9th data bit in the character to be transmitted when operating with serial
frames with 9 data bits. Must be written before writing the low bits to UDR.
USART Control and Status
Register C – UCSRC
Note that this register is not available in ATmega103 compatibility mode.
• Bit 7 - Reserved Bit
This bit is reserved for future use. For compatibility with future devices, these bit must be
written to zero when UCSRC is written.
• Bit 6 - UMSEL: USART Mode Select
This bit selects between asynchronous and synchronous mode of operation.
• Bit 5:4 - UPM1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the transmit-
ter will automatically generate and send the parity of the transmitted data bits within
each frame. The receiver will generate a parity value for the incoming data and compare
it to the UPM0 setting. If a mismatch is detected, the UPE flag in UCSRA will be set.
• Bit 3 - USBS: Stop Bit Select
This bit selects the number of stop bits to be inserted by the transmitter. The receiver
ignores this setting.
Bit
7
6
5
4
3
2
1
0
–
UMSEL
UPM1
UPM0
USBS
UCSZ1
UCSZ0
UCPOL
UCSRC
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
1
1
0
Table 77. UMSEL Bit Settings
UMSEL
Mode
0
Asynchronous Operation
1
Synchronous Operation
Table 78. UPM Bits Settings
UPM1
UPM0
Parity Mode
0
0
Disabled
0
1
(Reserved)
1
0
Enabled, Even Parity
1
1
Enabled, Odd Parity
Table 79. USBS bit Settings
USBS
Stop Bit(s)
0
1-bit
1
2-bits