Rainbow Electronics ATmega128L - Manual (Page 118)

118
ATmega128(L)
2467B–09/01
inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the output
should be set, cleared or toggle at a compare match (
See “Compare Match Output Unit”
on page 116.)
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 125.
Normal Mode The simplest mode of operation is the normal mode (WGMn3:0 = 0). In this mode the
counting direction is always up (incrementing), and no counter clear is performed. The
counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and
then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter over-
flow flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero.
The TOVn flag in this case behaves like a 17th bit, except that it is only set, not cleared.
However, combined with the timer overflow interrupt that automatically clears the TOVn
flag, the timer resolution can be increased by software. There are no special cases to
consider in the normal mode, a new counter value can be written anytime.
The input capture unit is easy to use in normal mode. However, observe that the maxi-
mum interval between the external events must not exceed the resolution of the counter.
If the interval between events are too long, the timer overflow interrupt or the prescaler
must be used to extend the resolution for the capture unit.
The output compare units can be used to generate interrupts at some given time. Using
the output compare to generate waveforms in normal mode is not recommended, since
this will occupy too much of the CPU time.
Clear Timer on Compare
Match (CTC) Mode In clear timer on compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn reg-
ister are used to manipulate the counter resolution. In CTC mode the counter is cleared
to zero when the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or
the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the counter,
hence also its resolution. This mode allows greater control of the compare match output
frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 50. The counter value
(TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then
counter (TCNTn) is cleared.
Figure 50. CTC Mode, Timing Diagram
An interrupt can be generated at each time the counter value reaches the TOP value by
either using the OCFnA or ICFn flag according to the register used to define the TOP
value. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing the TOP to a value close to BOTTOM when the
TCNTn
OCnA
(Toggle)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 4 Period 2 3
(COMnA1:0 = 1)