Rainbow Electronics ATmega128L - Manual (Page 100)

100
ATmega128(L)
2467B–09/01
Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the
compare match is ignored, but the set or clear is done at TOP. See “Phase Correct
PWM Mode” on page 95 for more details.
• Bit 2:0 - CS02:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see
Table 56.
Timer/Counter Register –
TCNT0
The Timer/Counter Register gives direct access, both for read and write operations, to
the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the
compare match on the following timer clock. Modifying the counter (TCNT0) while the
counter is running, introduces a risk of missing a compare match between TCNT0 and
the OCR0 register.
Output Compare Register –
OCR0
The Output Compare Register contains an 8-bit value that is continuously compared
with the counter value (TCNT0). A match can be used to generate an output compare
interrupt, or to generate a waveform output on the OC0 pin.
Table 55. Compare Output Mode, Phase Correct PWM Mode (1)
COM01 COM00 Description
0 0 Normal port operation, OC 0 disconnected.
0 1 Reserved
1 0 Clear OC 0 on compare match when up-counting. Set OC0 on compare
match when downcounting.
1 1 Set OC 0 on compare match when up-counting. Clear OC0 on compare
match when downcounting.
Table 56. Clock Select Bit Description
CS02 CS01 CS00 Description
0 0 0 No clock source (Timer/counter stopped)
0 0 1 clk
T0S
/(No prescaling)
0 1 0 clk
T0S
/8 (From prescaler)
0 1 1 clk
T0S
/32 (From prescaler)
1 0 0 clk
T0S
/64 (From prescaler)
1 0 1 clk
T0S
/128 (From prescaler)
1 1 0 clk
T 0 S
/256 (From prescaler)
1 1 1 clk
T 0 S
/1024 (From prescaler)
Bit 7 6 5 4 3 2 1 0
TCNT0[7:0] TCNT0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR0[7:0] OCR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0