Rainbow Electronics ATmega128L - Manual (Page 200)

200
ATmega128(L)
2467B–09/01
data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled
automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7..0 - TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte
received on the 2-wire Serial Bus.
TWI (Slave) Address Register
– TWAR
The TWAR should be loaded with the 7-bit slave address (in the seven most significant
bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or
receiver, and not needed in the master modes. In multimaster systems, TWAR must be
set in masters which can be addressed as slaves by other masters.
The LSB of TWAR is used to enable recognition of the general call address ($00). There
is an associated address comparator that looks for the slave address (or general call
address if enabled) in the received serial address. If a match is found, an interrupt
request is generated.
• Bits 7..1 - TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
• Bit 0 - TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus
events, like reception of a byte or transmission of a START condition. Because the TWI
is interrupt-based, the application software is free to carry on other operations during a
TWI byte transfer. Note that the TWI Interrupt Enable (TWIE) bit in TWCR together with
the Global Interrupt Enable bit in SREG allow the application to decide whether or not
assertion of the TWINT flag should generate an interrupt request. If the TWIE bit is
cleared, the application must poll the TWINT flag in order to detect actions on the TWI
bus.
When the TWINT flag is asserted, the TWI has finished an operation and awaits applica-
tion response. In this case, the TWI Status register (TWSR) contains a value indicating
the current state of the TWI bus. The application software can then decide how the TWI
should behave in the next TWI bus cycle by manipulating the TWCR and TWDR
registers.
Figure 94 is a simple example of how the application can interface to the TWI hardware.
In this example, a master wishes to transmit a single data byte to a slave. This descrip-
tion is quite abstract, a more detailed explanation follows later in this chapter. A simple
code example implementing the desired behaviour is also presented.
Bit 7 6 5 4 3 2 1 0
TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE TWAR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1 1 1 1 1 0