Altera Arria V Avalon-MM - Manual (Page 108)

Figure 7-2: Block Diagram for Custom Interrupt Handler
M
S
MSI/MSI-X IRQ
MSI-X Table Entries
S
Qsys
Interconnect
S
M
PCIe-Avalon-MM
Bridge
Hard
IP for
PCIe
MSI or
MSI-X
Req
IRQ Cntl
& Status
Table &
PBA
RXM
Custom
Interrupt Handler
Qsys System
MSI-X PBA
MsiIntfc_o[81:0]
MsiControl_o[15:0]
MsixIntfc_o[15:0]
IntxReq_i
IntxAck_o
PCIe
Root
Port
Refer to Interrupts for Endpoints for the definitions of MSI, MSI-X, and INTx buses.
For more information about implementing MSI or MSI-X interrupts, refer to the PCI Local Bus Specifica‐
tion, Revision 2.3, MSI-X ECN.
For more information about implementing interrupts, including an MSI design example, refer to
Handling PCIe Interrupts on the Altera wiki.
Related Information
• Interrupts for Endpoints on page 7-1
• PCI Local Bus Specification, Revision 2.3
• Handling PCIe Interrupts
7-4 Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI‑X
Support
UG-01105_avmm
2014.12.15
Altera Corporation Interrupts for Endpoints
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