Altera Arria V Avalon-MM User Manual

Page 30

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Parameter

Value

Description

Enable hard IP status bus

On/Off

When you turn this option on, your top-level variant

includes the signals necessary to connect to the

Transceiver Reconfiguration Controller IP Core, your

variant, including:
• Link status signals

• ECC error signals

• TX and RX parity error signals

• Completion header and data signals, indicating the

total number of Completion TLPs currently stored

in the RX buffer

Altera recommends that you include the Transceiver

Reconfiguration Controller IP Core in your design to

improve signal quality.

Enable hard IP status

extension bus

On/Off

When you turn this option on, your top-level variant

includes signals that are useful for debugging,

including link training and status, error, and the

Transaction Layer Configuration Space signals. The

top-level variant also includes signals showing the

start and end of packets, error, ready, and BAR signals

for the native Avalon-ST interface that connects to the

Transaction Layer. The following signals are included

in the top-level variant:
• Link status signals

• ECC error signals

• Transaction Layer Configuration Space signals

• Avalon-ST packet, error, ready, and BAR signals

Avalon to PCIe Address Translation Settings

Number of address pages

1, 2, 4, 8, 16, 32,

64, 128, 256, 512

Specifies the number of pages required to translate

Avalon-MM addresses to PCI Express addresses

before a request packet is sent to the Transaction

Layer. Each of the 512 possible entries corresponds to

a base address of the PCI Express memory segment of

a specific size. This parameter is only necessary when

you select 32-bit addressing.

Size of address pages

4 KBytes4

GBytes

Specifies the size of each memory segment. Each

memory segment must be the same size. Refer to

Avalon-MM-to-PCI Express Address Translation

Algorithm for 32-Bit Bridge for more information

about address translation. This parameter is only

necessary when you select 32-bit addressing.

UG-01105_avmm

2014.12.15

Avalon Memory‑Mapped System Settings

3-11

Parameter Settings

Altera Corporation

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