Altera Arria V Avalon-MM - Manual (Page 33)

Table 4-1: Avalon-MM CRA Slave Interface Signals
Signal Name Directio
n
Description
CraIrq_o Output Interrupt request. A port request for an Avalon-MM interrupt.
CraReadData_o[31:0] Output Read data lines
CraWaitRequest_o Output Wait request to hold off more requests
CraAddress_i[13:0] Input An address space of 16,384 bytes is allocated for the control
registers. Avalon-MM slave addresses provide address
resolution down to the width of the slave data bus. Because all
addresses are byte addresses, this address logically goes down
to bit 2. Bits 1 and 0 are 0.
CraByteEnable_i[3:0] Input Byte enable
CraChipSelect_i Input Chip select signal to this slave
CraRead_i Input Read enable
CraWrite_i Input Write request
CraWriteData_i[31:0] Input Write data
RX Avalon-MM Master Signals
This Avalon-MM master port propagates PCI Express requests to the Qsys interconnect fabric. For the
full-feature IP core it propagates requests as bursting reads or writes. A separate Avalon-MM master port
corresponds to each BAR.
Table 4-2: Avalon-MM RX Master Interface Signals
Signals that include Bar number 0 also exist for BAR1–BAR5 when additional BARs are enabled.
Signal Name Direction Description
RxmWrite<n> Output Asserted by the core to request a write to an Avalon-
MM slave.
RxmAddress_<n>_o[31:0] Output The address of the Avalon-MM slave being accessed.
RxmWriteData_<n>_o[<w>-1:0] Output RX data being written to slave. <w> = 64 or 128 for the
full-featured IP core. <w> = 32 for the completer-only
IP core.
UG-01105_avmm
2014.12.15
RX Avalon-MM Master Signals 4-3
Interfaces and Signal Descriptions Altera Corporation
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