Altera Arria V Avalon-MM - Manual (Page 17)

9. From the Simulation list, select ModelSim ® . From the Format list, select the HDL language you
intend to use for simulation.
10.Click Next to display the Summary page.
11.Check the Summary page to ensure that you have entered all the information correctly.
12.Click Finish to create the Quartus II project.
13.Add the Synopsys Design Constraint (SDC) commands shown in the following example to the
top-level design file for your Quartus II project.
14.To compile your design using the Quartus II software, on the Processing menu, click Start Compila‐
tion. The Quartus II software then performs all the steps necessary to compile your design.
15.After compilation, expand the TimeQuest Timing Analyzer folder in the Compilation Report. Note
whether the timing constraints are achieved in the Compilation Report.
16.If your design does not initially meet the timing constraints, you can find the optimal Fitter settings for
your design by using the Design Space Explorer. To use the Design Space Explorer, click Launch
Design Space Explorer on the tools menu.
Example 2-1: Synopsys Design Constraints
create_clock -period “100 MHz” -name {refclk_pci_express}{*refclk_*}
derive_pll_clocks
derive_clock_uncertainty
# PHY IP reconfig controller constraints
# Set reconfig_xcvr clock
# Modify to match the actual clock pin name
# used for this clock, and also changed to have the correct period set
create_clock -period "125 MHz" -name {reconfig_xcvr_clk}{*reconfig_xcvr_clk*}
2-6 Compiling the Design in the Quartus II Software
UG-01105_avmm
2014.12.15
Altera Corporation Getting Started with the Avalon‑MM Arria V Hard IP for PCI Express
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