Altera Arria V Avalon-MM - Manual (Page 9)

Debug Features
Debug features allow observation and control of the Hard IP for faster debugging of system-level
problems.
Related Information
Debugging on page 13-1
IP Core Verification
To ensure compliance with the PCI Express specification, Altera performs extensive verification. The
simulation environment uses multiple testbenches that consist of industry-standard bus functional
models (BFMs) driving the PCI Express link interface. Altera performs the following tests in the
simulation environment:
• Directed and pseudorandom stimuli are applied to test the Application Layer interface, Configuration
Space, and all types and sizes of TLPs
• Error injection tests that inject errors in the link, TLPs, and Data Link Layer Packets (DLLPs), and
check for the proper responses
• PCI-SIG ® Compliance Checklist tests that specifically test the items in the checklist
• Random tests that test a wide range of traffic patterns
Altera provides the following two example designs that you can leverage to test your PCBs and complete
compliance base board testing (CBB testing) at PCI-SIG.
Related Information
• PCI SIG Gen3 x8 Merged Design - Stratix V
• PCI SIG Gen2 x8 Merged Design - Stratix V
Compatibility Testing Environment
Altera has performed significant hardware testing to ensure a reliable solution. In addition, Altera
internally tests every release with motherboards and PCI Express switches from a variety of manufac‐
turers. All PCI-SIG compliance tests are run with each IP core release.
Performance and Resource Utilization
Because the PCIe protocol stack is implemented in hardened logic, it uses less than 1% of device
resources.
The Avalon-MM bridge is implemented in soft logic and functions as a front end to the hardened
protocol stack. The following table shows the typical device resource utilization for selected configura‐
tions using the current version of the Quartus II software. With the exception of M10K memory blocks,
the numbers of ALMs and logic registers in the following tables are rounded up to the nearest 50.
1-8 Debug Features
UG-01105_avmm
2014.12.15
Altera Corporation Datasheet
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