Altera Arria V Avalon-MM - Manual (Page 91)

Table 5-24: Avalon‑MM Interrupt Status Registers for Root Ports, 0x3060
Bits Name Access
Mode
Description
[31:5] Reserved — —
[4] RPRX_CPL_RECEIVED RW1C Set to 1’b1 when the Root Port has
received a Completion TLP for an
outstanding Non-Posted request from
the TLP Direct channel.
[3] INTD_RECEIVED RW1C The Root Port has received INTD from
the Endpoint.
[2] INTC_RECEIVED RW1C The Root Port has received INTC from
the Endpoint.
[1] INTB_RECEIVED RW1C The Root Port has received INTB from
the Endpoint.
[0] INTA_RECEIVED RW1C The Root Port has received INTA from
the Endpoint.
Table 5-25: INT‑X Interrupt Enable Register for Root Ports, 0x3070
Bit Name Access
Mode
Description
[31:5] Reserved — —
[4] RPRX_CPL_RECEIVED RW When set to 1’b1, enables the assertion
of
CraIrq_o
when the Root Port
Interrupt Status register
RPRX_CPL_
RECEIVED
bit indicates it has received a
Completion for a Non-Posted request
from the TLP Direct channel.
[3] INTD_RECEIVED_ENA RW When set to 1’b1, enables the assertion
of
CraIrq_o
when the Root Port
Interrupt Status register
INTD_
RECEIVED
bit indicates it has received
INTD.
UG-01105_avmm
2014.12.15
PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 5-29
Registers Altera Corporation
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