Physical layer interface signals, Transceiver reconfiguration – Altera Arria V Avalon-MM User Manual
Page 45
Figure 4-4: Legacy Interrupt Deassertion
clk
IntxReq_i
IntAck_o
Physical Layer Interface Signals
Altera provides an integrated solution with the Transaction, Data Link and Physical Layers. The IP
Parameter Editor generates a SERDES variation file,
<variation>_serdes.v
or .vhd , in addition to the Hard
IP variation file,
<variation>.v
or
.vhd
. The SERDES entity is included in the library files for PCI Express.
Transceiver Reconfiguration
Dynamic reconfiguration compensates for variations due to process, voltage and temperature (PVT).
Among the analog settings that you can reconfigure are V
OD
, pre-emphasis, and equalization.
You can use the Altera Transceiver Reconfiguration Controller to dynamically reconfigure analog
settings. For Gen2 operation, you must turn on Enable duty cycle calibration in the Transceiver Reconfi‐
guration Controller GUI. Arria V devices require duty cycle calibration (DCD) for data rates greater than
4.9152 Gbps. For more information about instantiating the Altera Transceiver Reconfiguration Controller
IP core refer to Hard IP Reconfiguration .
Table 4-8: Transceiver Control Signals
In this table, <n> is the number of interfaces required.
Signal Name
Direction
Description
reconfig_from_
xcvr[(<n>46)-1:0]
Output
Reconfiguration signals to the Transceiver Reconfiguration
Controller.
reconfig_to_xcvr[(<n>
70)-1:0]
Input
Reconfiguration signals from the Transceiver Reconfiguration
Controller.
busy_xcvr_reconfig
Input
When asserted, indicates that the a reconfiguration operation is
in progress.
reconfig_clk_locked
Output
When asserted, indicates that the PLL that provides the fixed
clock required for transceiver initialization is locked. The
Application Layer should be held in reset until
reconfig_clk_
locked
is asserted.
The following table shows the number of logical reconfiguration and physical interfaces required for
various configurations. The Quartus II Fitter merges logical interfaces to minimize the number of physical
interfaces configured in the hardware. Typically, one logical interface is required for each channel and one
for each PLL.
UG-01105_avmm
2014.12.15
Physical Layer Interface Signals
4-15
Interfaces and Signal Descriptions
Altera Corporation